XC50256 CXL 2.0 Switch Chip
Key features:
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Fully compliant with CXL2.0/1.1 and PCIE Gen5
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Support CXL.io, CXL.mem and CXL.cache
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CXL1.1 and CXL2.0 Fabric Manager Interface Support MLD (Multiple Logic Device)
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Multiple virtual CXL switches (VCS)
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Support CXL Type2 and Type 3 memory devices
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Total up to 32 ports with Bifurcation
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Full RAS support (ECC/Parity, DPC, Hot-Plug, Data Poisoning)
World's First CXL 2.0 and PCIe Gen 5.0 Switch Chip
256 lanes with total 2,048GB/s switching capacity
Lowest port to port latency
Low power consumption/port
Reduced PCB area
Lower TCO
XC51256 PCIe Gen 5.0 Switch Chip
Key features:
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Fully compliant with PCIe Gen 5.0 Specification
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Lowest-latency PCIe Gen 5.0 switch in the market
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Largest PCIe switch in the market with 256 lanes enables higher number of fanout connectivity
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x8 and x16 port-bifurcation enables up to 32 ports or 16 ports, respectively (or a combination of x8 and x16 ports, not exceeding 256 lanes)
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Supports Virtual Switches, Non-Transparent Bridges and Multi-host IO Sharing
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Supports hot-plug, hot-add, hot-remove and surprise-plug
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Supports diagnostics with Embedded Logic Analyzer (ELA) and Debug GUI
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I2C, SPI, UART, GPIO, JTAG, SRIS/SRNS
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