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Job Title: ASIC Design Verification Engineer
San Jose, California
Provide design verification services for our SoC
Responsibilities:
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Test bench development using System Verilog UVM
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Test plan and test case development with functional coverage, assertion, coverage property, coverage groups and coverage collections
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Regression setup and debug at RTL level and gate sim level working with design team
Requirements:
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10+ Design Verification experience
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Deep knowledge about System Verilog, UVM and verification coverage matrix
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Familiar with Synopsys PCIe/CXL VIP and Mentor Graphics QVIP
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Strong experience with PCIe/CXL protocol (PHY/DLLP/TLP)
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Very familiar with the peripheral protocols such as UART, I2C, SPI Flash
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Proficient in Perl scripting
Job Title: ASIC Design Engineer
San Jose, California
Provide design services for our SoC
Responsibilities:
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Participate in architecture definition and modeling.
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Contribute to micro-architecture specification and reviews.
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Review industry standard specs and ensure IPs are kept up to date for compliance.
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Define design partitioning for efficient IP/sub-system/full chip implementation.
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Review and provide feedback on verification plans and methodology.
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Drive block/chip/system level development and execution.
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Work with Hard IP designers, verification, validation, Firmware engineers and architects to produce thoroughly verified, robust IP.
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Actively participate in post-silicon bring-up, validation and compliance testing.
Requirements:
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10 – 15 years of experience in logic design using Verilog/System Verilog
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Proven track record of taking several chips in from product definition to production.
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Experience in complex ASIC design.
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Good understanding of ASIC design and verification methodologies and flows.
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Excellent understanding of standard ASIC design techniques, including:
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Architecture/Micro-architecture definition
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Design partitioning and Hard IP interactions
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Multiple async clock domain designs
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Design for test
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Clock/Reset
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Power aware
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Excellent understanding of Synthesis, STA, CDC, Lint, LEC
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Very strong domain knowledge about PCIe/CXL
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Very familiar with the peripheral protocols such as UART, I2C, SPI Flash
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Proficient in Perl scripting