Laptop Typing

JOIN THE TEAM

Job Openings

Job Title: ASIC Design Verification Engineer

                    San Jose, California

Provide design verification services for our SoC

Responsibilities:

  • Test bench development using System Verilog UVM

  • Test plan and test case development with functional coverage, assertion, coverage property, coverage groups and coverage collections

  • Regression setup and debug at RTL level and gate sim level working with design team

 

Requirements:

  • 10+ Design Verification experience

  • Deep knowledge about System Verilog, UVM and verification coverage matrix

  • Familiar with Synopsys PCIe/CXL VIP and Mentor Graphics QVIP

  • Strong experience with PCIe/CXL protocol (PHY/DLLP/TLP)

  • Very familiar with the peripheral protocols such as UART, I2C, SPI Flash

  • Proficient in Perl scripting

Job Title: ASIC Design Engineer

                    San Jose, California

Provide design services for our SoC

Responsibilities:

  • Participate in architecture definition and modeling.

  • Contribute to micro-architecture specification and reviews.

  • Review industry standard specs and ensure IPs are kept up to date for compliance.

  • Define design partitioning for efficient IP/sub-system/full chip implementation.

  • Review and provide feedback on verification plans and methodology.

  • Drive block/chip/system level development and execution.

  • Work with Hard IP designers, verification, validation, Firmware engineers and architects to produce thoroughly verified, robust IP.

  • Actively participate in post-silicon bring-up, validation and compliance testing.

 

Requirements:

  • 10 – 15 years of experience in logic design using Verilog/System Verilog

  • Proven track record of taking several chips in from product definition to production.

  • Experience in complex ASIC design.

  • Good understanding of ASIC design and verification methodologies and flows.

  • Excellent understanding of standard ASIC design techniques, including:

  • Architecture/Micro-architecture definition

  • Design partitioning and Hard IP interactions

  • Multiple async clock domain designs

  • Design for test

  • Clock/Reset

  • Power aware

  • Excellent understanding of Synthesis, STA, CDC, Lint, LEC

  • Very strong domain knowledge about PCIe/CXL

  • Very familiar with the peripheral protocols such as UART, I2C, SPI Flash

  • Proficient in Perl scripting

Send your resumes to hr@xconn-tech.com