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Job Openings

ASIC Design Verification Engineer

San Jose, California

Provide design verification services for our SoC

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Responsibilities:

  • Test bench development using System Verilog UVM

  • Test plan and test case development with functional coverage, assertion, coverage property, coverage groups and coverage collections

  • Regression setup and debug at RTL level and gate sim level working with design team

 

Requirements:

  • 10+ Design Verification experience

  • Deep knowledge about System Verilog, UVM and verification coverage matrix

  • Familiar with Synopsys PCIe/CXL VIP and Mentor Graphics QVIP

  • Strong experience with PCIe/CXL protocol (PHY/DLLP/TLP)

  • Very familiar with the peripheral protocols such as UART, I2C, SPI Flash

  • Proficient in Perl scripting

Principal Design Engineer

San Jose, California

Xconn-technologies Inc is a Silicon Valley based company working on the world’s leading edge PCIe & CXL Switch for AI/ML & Data center applications. Xconn-technologies is seeking a highly motivated & Passionate Principal design engineer to lead a PCIe/CXL switch subsystem design.

 

Job Description:

As a Principal ASIC design engineer, you will lead a part of innovative & advanced design of PCIe & CXL switches for HPC, AI/ML & Data centers. Your primary job is to work closely with architecture team to write micro-architecture specifications from an architecture spec.  The job also includes RTL design & helping the design verification test plan as well as preparing design constraints.  It is expected to run Lint & Synthesis to ensure RTL quality.  Once RTL is complete, you will be supporting the physical design timing closure & assisting the verification team to debug the design.

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Responsibilities:

  • Participate in architecture definition and modeling.

  • Contribute to micro-architecture specification and reviews.

  • Review industry standard specs and ensure IPs are kept up to date for compliance.

  • Define design partitioning for efficient IP/sub-system/full chip implementation.

  • Review and provide feedback on verification plans and methodology.

  • Drive block/chip/system level development and execution.

  • Work with Hard IP designers, verification, validation, Firmware engineers and architects to produce thoroughly verified, robust IP.

  • Actively participate in post-silicon bring-up, validation and compliance testing.

 

Requirements:

  • 10 – 15 years of experience in logic design using Verilog/System Verilog

  • Proven track record of taking several chips in from product definition to production.

  • Experience in complex & high gate count ASIC design.

  • Experience in PCIe or Ethernet switch or PCIe, CXL controller development is a big plus

  • Good understanding of ASIC design and verification methodologies and flows.

  • Architecture/Micro-architecture definition

  • Design partitioning and Hard IP integration & interactions

  • Multiple async clock domain designs

  • Experience with Clock/Reset trees, & DFT

  • Excellent understanding of Synthesis, STA, CDC, Lint, LEC

  • Familiarity with the peripheral protocols such as UART, I2C, SPI Flash

  • Proficient in Perl scripting

Principal Synthesis Design Engineer

San Jose, California

Xconn-technologies Inc is a Silicon Valley based company working on the world’s leading edge PCIe & CXL Switch. Xconn-technologies is seeking a highly motivated & Passionate Principal design engineer to lead its ASIC front to back activities for Synthesis, Prime time, design constraints development.

Job Description:

As an ASIC front to back design lead, you will lead the establishing & maintaining Synthesis, STA, Equivalency flows.  You will be working with the ASIC design engineers to ensure high quality RTL, design constraints & Netlist preparation to hand off to a third-party physical design company.  You will be responsible for ensuring the physical design partner receives Netlist & assist them with the design constraints issues as well as overseeing the floor planning, place & route & CDC placements.  Once the Place & Route is complete, you will receive the post-layout Netlist to resolve the timing closure issues. PCIe/CXL switch chips have a high gate count & require a deep understanding of hierarchical Synthesis.

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Responsibilities:

  • Build flows for methodologies incorporating front to back flow for Lint, Synthesis, prime time timing analysis, CDC & equivalency check.

  • Writing scripts & establishing automation for Synthesis & Prime time tools.

  • Provide support for ASIC tools and flows

  • Work with 3rd party vendor with the Netlist hand-off & oversee the physical design & ensure a clean tape out.

  • Full chip & block level timing constraints ensuring area & timing optimization

  • Implement functional ECOs

  • Monitoring DFT insertion for scan, memory Bist & Loopback tests mechanisms.

 

Requirements:

  • BS or MS in Electrical or Computer engineering.

  • 10+ years of experience in chip development & familiarity with ASIC CAD & EDA tools

  • Knowledge with Synopsys synthesis & STA tools.

  • Experience with high gate count ASICs

  • Experience with ASIC methodologies such as Verilog design, Lint, Synthesis, STA & DFT.

  • Strong track record of hierarchical synthesis, STA, Lint, CDC & LEC methodologies,

  • Strong experience in design constraints

  • Solid experience in Hierarchical Synthesis & Static timing analysis.

  • Proficiency in Perl scripting for automation.

Send your resume to:

hr@xconn-tech.com

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